Título/s: | Finding operating points in networks containing MOS transistors by a piecewise-linear approach |

Autor/es: | Jiménez-Fernández, Víctor M.; Julián, Pedro Marcelo; Agamenoni, Osvaldo; Di Federico, Martín; Hernández-Martínez, Luis; Samiento-Reyes, Arturo |

Institución: | Universidad Nacional del Sur. Bahía Blanca, AR INTI-Centro de Micro y Nano Electrónica del Bicentenario. CMNB. Buenos Aires, AR Instituto Nacional de Astrofísica, Óptica y Electrónica. INAOE. Puebla, MX |

Editor: | s.e. |

Palabras clave: | Transistores; Redes eléctricas; Resistores; Voltaje; Corriente continua |

Idioma: | eng |

Fecha: | 2007 |

Ver+/- XII Reunio´n de Trabajo en Procesamiento de la Informaci o´n y Control, 16 al 18 de octubre de 2007
Finding operating points in networks containing MOS transistors by a piecewise-linear approach Vı´ctor M. Jime´nez-Ferna´ndez, Pedro Marcelo Julia´n, Osvaldo Agamenoni and Martı´n Di Federico † Luis Herna´ndez-Matı´nez and Arturo Samiento-Reyes‡ †Universidad Nacional del Sur, Bahı´a Blanca, Argentina vjimenez@inaoep.mx ‡Instituto Nacional de Astrofı´sica, ´Optica y Electro´nica, Me´xico. luish@inaoep.mx Abstract— In this paper we present a method- ology for finding operating points in networks con- taining MOS transistors, linear positive resistors, and independent voltage and current sources. The MOS transistors are described by the high-canonical piecewise-linear (HC-PWL) model. A hybrid for- mulation is obtained from the network under anal- ysis and it is solved in order to find the solution(s). The methodology takes advantage from the uniformly spaced simplicial partition in which the HC-PWL model is based because it makes possible to apply the Kuh-Chien algorithm. This algorithm has proved its efficiency to solve nonlinear resistive networks into simplicial subdivision schemes. Keywords— DC solutions, Simplicial partition, High canonical piecewise-linear, MOS transistor net- works I INTRODUCTION The task of finding the operating points, in networks con- taining elements which are described by piecewise-linear (PWL) models, is a topic of interest in nonlinear circuit theory. Although numerous important references about PWL modeling and analysis can be found [1]- [4], there are not reported techniques which deal with the problem of applying the HC-PWL to DC analysis, and specifically with the task of computing operating points. This paper intends to be a first draft to overcome such problem. The main contribution of this paper is a methodology which is based on the Kuh-Chien algorithm [9], for computing operating points by a PWL approach where the nonlin- ear elements are described by the HC-PWL model. The network under study is considered to include MOS tran- sistors which are described by the two dimensional HC- PWL model reported by Julia´n “et al.” in references [5] and [6]. Such model describes a n-dimensional PWL function f(x) by the analytical expression f(x) = CTΛ(x), ∀x ∈ S Defined over a rectangular compact domain S in Rn S = {(x1, · · · , xn) : 0 ≤ xi ≤ miδ, i ∈ {1, · · · , n}} when δ is a parameter called the grid step and mi defines the rectangular length which is simplex partitioned. C is denoted as vector of parameters and Λ is an expres- sion which contains terms described by the so called ab- solute value γ function that is given by γ (fi, fj) = 14 {||−fi|+ fj | − |−fi + |fj||} + 1 4 {|−fi|+ |fj | − |−fi + fj|} with fi and fj as hyperplane equations. A more detailed explanation about the HC-PWL model can be found in references [5], [6], and [7]. In this paper we are specifically interested in a methodology for computing operating points that is compatible with the HC-PWL model. The model description of the MOS transistors is assumed to be the explicit form of the HC-PWL representation reported in [7]. II MOS TRANSISTOR NETWORK Fig.1 shows a 2µ-port network terminated by µ MOS transistors. In the network there are linear positive re- sistors and independent voltage and current sources. + _ _ + vDS1 vGS1 iDS1 iGS1 . . . + _ _ + iDS(2µ-1) vDS (2µ-1) vGS (2µ) iGS(2µ) Figure 1: A 2µ port terminated by MOS transistors. XII Reunio´n de Trabajo en Procesamiento de la Informaci o´n y Control, 16 al 18 de octubre de 2007
A hybrid formulation for the 2µ-port is reported in refer- ence [8] and it is given by[ iα vβ ] = − [ Hαα Hαβ Hβα Hββ ] [ vα iβ ] + [ dα dβ ] (1) where iα = [ iDS1 · · · iDS(2µ−1) ]T , iβ = [ iGS2 · · · iGS(2µ) ]T , vα = [ vDS1 · · · vDS(2µ−1) ]T ,vβ = [vGS2 · · · vGS(2µ)]T are port currents and port voltages, dα, dβ are subvectors of source vector. From the MOS physics characteristics it can be seen that iα = f (vα,vβ) and iβ = 0. So that the hybrid formula- tion is reduced to: f (vα,vβ) +Hααvα = dα (2) Hβαvα + vβ = dβ (3) III TWO DIMENSIONAL SIMPLICIAL SUBDIVISION In the network shown in Fig.1, it is considered that the functions iα = f (vα, vβ) are defined over a simplicial partition space. Hence, it is important to introduce the notation that here after will be used to refer the simplices. Figure 2 shows a two-dimensional space which has been simplically partitioned. x1 x2 x0 Figure 2: A two-dimensional simplicial partition. Let x0,x1,x2 be three points in this space. A simplex S (x0,x1,x2) is defined by S = (x0,x1,x2) = { x : x = 2∑ i=0 µixi } (4) with 1 ≥ µi ≥ 0, i = {0, 1, 2} and ∑2 i=0 µi = 1 The points x0,x1, and x2 are called vertices of the simplex. Corresponding to three vertices, there are three boundaries Bk. Bk contains all the vertices except xk and it is defined as Bk = {x : x ∈ S (x0,x1,x2)} (5) with µk = 0, and k = {0, 1, 2} The intersection of two boundaries is called corner. Thus every vertex is in fact a corner. Fig.3 depicts the geometrical relation between the vertices and boundaries for any simplex in a two-dimensional space. x2 x1x0 B1 B0 B2 Figure 3: S = (x0,x1,x2) and its boundaries. IV REPLACEMENT RULE In reference [9], Kuh and Chien proposed a technique denominated replacement rule. It permits to trace a path in a structure of simplices. The technique considers that a new simplex can be reached by deleting a vertex and crossing its boundary. This idea is graphically depicted in Fig.4. x2 x1x0 B1 x1 Figure 4: Replacement rule. Let the boundaries set be defined by Bk = { x : [ x 1 ] = [ x0 x1 x2 1 1 1 ]} µ (6) where the k-th component of µ is zero, (µk = 0) The new region is determined by the boundary B k, and a new vertex xˆk is computed from xˆ = xk+1 + xk−1 − xk (7) with k = 1 at reference value Equation (7) is usefull in the iterative process of finding an operating point, because it indicates how to traverse simplices until the solution is reached. V THE KUH-CHIEN ALGORITHM Let the two-dimensional equation Y(x) = G (x) be de- fined on a finite simplicial partition domain. Let S (x0,x1,x2) be any simplex in a simplicial parti- tion. An affine function approximating the given g(·) on S (x0,x1,x2) can be defined by Y (x) = [g (x0) ,g (x1) ,g (x2)]µ (8) for x ∈ S (x0,x1,x2) and µ = [µ0, µ1, µ2]T Let adopt the following representation:[ Y(x) 1 ] = [ g (x0) g (x1) g (x2) 1 1 1 ] µ (9) XII Reunio´n de Trabajo en Procesamiento de la Informaci o´n y Control, 16 al 18 de octubre de 2007
for x ∈ S (x0,x1,x2) with[ x 1 ] = [ x0 x1 x2 1 1 1 ] µ (10) Then, equation (9) can be rewritten as[ Y(x) 1 ] = [ g (x0) g (x1) g (x2) 1 1 1 ] Xµ (11) with Xµ = [ x0 x1 x2 1 1 1 ] −1 [ x 1 ] (12) Since x ∈ S (x0,x1,x2) if and only if the vector µ sat- isfies the condition 1 ≥ µ ≥ 0, then it is very easy to check whether an approximate solution of Y = G(x), is found in S (x0,x1,x2) if and only if the solution of eq. (9) satisfies µ ≥ 0. If there exists any negative element in µ, then the solution must be reached in other simplex. It implies an iterative process of solving eq.(9) and checking µ. Aided by the replacement rule, the new region which the solution en- ters is easily determined. VI METHODOLOGY Let a nonlinear network containing linear resistors, inde- pendent voltage sources, independent current sources and MOS transistors be described by the HC-PWL model as a the analytical PWL function iDS = CTΛ(vDS , vGS). The methodology for finding operating points is summa- rized in the following steps: • Step 1: Obtain the reduced hybrid formulation for the network depicted in Fig. 1 as f (vα,vβ) +Hααvα = dα (13) Hβαvα + vβ = dβ (14) where f (vα,vβ) has the form CTΛ(vDS , vGS) • Step 2: Recast the reduced hybrid formulation into the form Y = 0 as Y = [ f (vα,vβ) +Hααvα − dα Hβαvα + vβ − dβ ] = 0 (15) • Step 3: Start with the simplex: {x0,x1,x2} • Step 4: Evaluate the simplex vertices into the sys- tem Y(x) = G(x) = 0 Y(x) = [g (x0) ,g (x1) ,g (x2)] = 0 (16) • Step 5: Form the system for the i-th iteration[ Y(x) 1 ] = [ G (x) 1 ] µ(i) = [ 0 1 ] (17) with µ(i) = µ (i) 0 µ(i)1 µ(i)2 = [ µ(i)0 , · · · , µ(i)k ]T (18) and k ∈ {0, 1, 2} • Step 6 Solve equation (17) for µ(i) • Step 7: Search the k-th element of µ(i) which is negative. If all the elements of µ(i) are positive, then go to Step 9, otherwise go to Step 8 • Step 8: Apply the replacement rule to the xk vertex and return to Step 3 x˜k = xk+1 + xk−1 − xk (19) • Step 9: The solution is found. Compute the solu- tion by [x] = [ x0 x1 x2 ]µ(i) (20) The above methodology is applied repeatedly in order to compute various operating points. VII CASE STUDY The latch circuit shown in Fig.5 is a well known three operating points circuit. We are interested in computing these solutions by applying the simplicial methodology presented in the previous section. This circuit contains two nMOS transistors, two linear re- sistors (R1 and R2) and a voltage source (VDD). VDD GND R1 R2 0 1 2 iDS1 iDS2 Figure 5: Example circuit. The nMOS transistors are described by the two dimen- sional HC-PWL model. In order to make more legible the HC-PWL formulation for iDS , the following notation is introduced δba = a |vDS − b| φba = a |vGS − b| γba = a |vDS − vGS + b| λb,ca = a ||vGS − b|+ vDS − c| −a |−vGS + b+ |vDS − c|| And iDS is given by iDS = 1 4 {HPWL} µA XII Reunio´n de Trabajo en Procesamiento de la Informaci o´n y Control, 16 al 18 de octubre de 2007
where HPWL = δ332 + δ0125 + δ4−24 + δ112 + δ2−14 + φ412 + φ328 +φ257 + λ1,11 + λ3,2−13 + λ4,4−25 + λ3,1−26 + λ2,19 + λ2,0−50 +λ3,043 + λ 3,3 23 + λ 4,0 2 + λ 1,0 30 + λ 4,1 28 + λ 1,4 1 + λ 4,3 9 +λ4,2 −2 + λ 1,3 1 + λ 2,3 −1 + λ 3,4 1 + λ 2,4 −1 + λ 1,2 1 + λ 2,0 50 The piecewise linear function iDS is described over an uniformly spaced grid within a finite rectangular region defined by 0 ≤ vDS ≤ 5 and 0 ≤ vGS ≤ 5 as shown in Fig.6. The grid vDS − vGS is divided into a set of 1V squares and it is subdivided into a simplicial partition. Figure 6: iDS piecewise-linear curve. The data points in Fig.6 follow the Shichman-Hodges model [10]; namely iDS = ˜K [ (vGS − Vt) vDS − 12v 2 DS ] if vDS ≤ vGS − Vt; or iDS = 1 2 ˜K (vGS − Vt)2 [ 1 + ˜λ (vDS − vGS + Vt) ] if vDS > vGS − Vt, with ˜K = 50µA/V 2, Vt = 1V and ˜λ = 0.0V −1. From Fig.5, the following nodal information is collected node1 : iDS1 + vDS1 − VDD R1 = 0, vDS1 = vGS2 (21) node2 : iDS2 + vDS2 − VDD R2 = 0, vDS2 = vGS1 (22) Because of iDS1 = f(vDS1, vGS1) and iDS2 = f(vDS2, vGS2), then the above equations can be rewrit- ten into the reduced hybrid system format as f (vDS1, vGS1) + ( 1 R1 ) vDS1 = VDD R1 (23) f (vDS2, vGS2) + ( 1 R2 ) vDS2 = VDD R2 (24) vDS1 − vGS2 = 0 vDS2 − vGS1 = 0 Notice that equation (23) and equation (24) can be recast as f (e1, e2) + ( 1 R1 ) e1 = VDD R1 (25) f (e2, e1) + ( 1 R2 ) e2 = VDD R2 (26) where e1 and e2 are nodal voltages. From equation (25) and equation (26), it can be defined the equation system Y = 0 as y1 = iDS (e1, e2) + ( e1 − VDD R1 ) = 0 (27) y2 = iDS (e2, e1) + ( e2 − VDD R2 ) = 0 (28) Let R1 = R2 = 30KΩ and VDD = 3.3V . The solutions of the system Y = 0 are computed as follows. Firstly, a start simplex is chosen. Let x0 = [ 2 4 ] , x1 = [ 2 5 ] , x2 = [ 3 5 ] (29) The equation to be solved at the first iteration is g1(x0) g1(x1) g1(x2)g2(x0) g2(x1) g2(x2) 1 1 1 µ(i) = 00 1 (30) After substituting it yields [ G (x) 1 ] µ(0) = 00 1 (31) G (x) = [ 14.37 21.67 30 5.63 9.09 18.06 ] × 10−5 (32) The solution is µ(0) = µ (0) 0 µ(0)1 µ(0)2 = 3.22 −2.44 0.22 (33) Since µ01 is negative, then the vertex x1 must be replaced by [ 2 4 ] + [ 3 5 ] − [ 2 5 ] = [ 3 4 ] (34) The new simplex is defined by[ 2 4 ] , [ 3 4 ] , [ 3 5 ] XII Reunio´n de Trabajo en Procesamiento de la Informaci o´n y Control, 16 al 18 de octubre de 2007
In this simplex, the new equation to solve is[ G (x) 1 ] µ(1) = 00 1 (35) G (x) = [ 14.37 20.5 30 5.63 14.6 18.06 ] × 10−5 (36) The solution is µ(1) = µ (1) 0 µ(1)1 µ(1)2 = 1.0651.405 −1.47 (37) And the vertex to be replaced is x2 by [2 3]T . The new simplex is then defined by[ 2 4 ] , [ 3 4 ] , [ 2 3 ] The results in the third, fourth, and fifth iteration are µ(2) = µ (2) 0 µ(2)1 µ(2)2 = −1.7090.295 2.414 (38) with the following simplex defined in[ 3 3 ] , [ 3 4 ] , [ 2 3 ] µ(3) = µ (3) 0 µ(3)1 µ(3)2 = 0.93 −0.855 0.918 (39) and the new simplex defined in[ 3 3 ] , [ 2 2 ] , [ 2 3 ] µ(4) = µ (4) 0 µ(4)1 µ(4)2 = 0.0990.9 0 (40) Since µ4 > 0, there is not following simplex to jump, then the solution is computed by[ e1 e2 ] = [ 3 2 2 3 2 3 ] µ(4) = [ 2.099 2.099 ] (41) After applying the same algorithm into two different start simplices, the following solutions can be computed[ e1 e2 ] = [ 1 0 1 3 3 4 ] µ(4) = [ 0.857 3.3 ] (42) [ e1 e2 ] = [ 3 3 4 0 1 1 ] µ(5) = [ 3.3 0.857 ] (43) Notice that the three computed solutions can be sub- stituted into the eq.(25) and eq.(26) and the condition Y = 0 is fullfil. The paths followed by the algorithm to obtain the solutions are depicted in Fig.7. vDS vGS start start start solution solution solution 0 1 2 3 4 5 1 2 3 4 5 Figure 7: Path solutions into the simplicial partition. VIII Conclusions A methodology for finding operating points in networks containing MOS transistors was proposed. Such method- ology is based into the Kuh-Chien algorithm and it is able to handle equation systems which involve the HC-PWL description. Because the algorithm is able to compute only one solution, in multiple operating point systems it is necessary to apply it as many times as solutions exists. It presents two important challenges, the first consists in determining previously to the analysis, the maximum number of existing solutions of the system. The other one consists in determining the optimal starting point for running the Kuh-Chien algorithm. The analysis of both problems promise interesting results in this topic under investigation IX Aknowledgment This work was partially funded by project PICT 2003 No.13468 of ANPCyT. Ph.D. Vı´ctor M. Jime´nez Ferna´ndez is grateful for the partial economical support that he received by the Na- tional Institute for Astrophysics, Optics and Electronics (Me´xico) in his Post.Ph.D. visitor position at the Univer- sidad Nacional del Sur, Bahı´a Blanca, Argentina. REFERENCES [1] L.O. Chua, A. Deng, “Canonical Piecewise-Linear Modeling ”, Transactions on Circuits and Systems, VOL. CAS-33, May, 1986. [2] L.O. Chua, L.P. Ying,“Canonical Piecewise-Linear Analysis ”, Transactions on Circuits and Systems, VOL. CAS-30, March, 1983. [3] W.M.G. van Bokhoven, “Piecewise Linear Modelling and Analysis ”, Kluwer Academic Press, 1998. [4] J. Brzobohaty, J. Pospisil, and Z. Kolka,“Decomposed parametric form of the state model of piecewise linear systems”, IEEE London section, s. 1-9, 1977. XII Reunio´n de Trabajo en Procesamiento de la Informaci o´n y Control, 16 al 18 de octubre de 2007
[5] P. Julia´n, “High-Level Canonical Piecewise Linear Representation: Theory and Applications,” Ph.D. Thesis, Universidad Nacional del Sur, Bahı´a Blanca, Argentina, pp. 463-480, May 1999. [6] P. Julia´n and O. Agamennoni, “High-Level Canon- ical Piecewise Linear Representation Using a Sim- plicial Partition,” IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, VOL.46, pp. 463-480, April 1999. [7] P. Julia´n, A. Desages, and B. D’Amico, “ Orthonor- mal High-Level Canonical PWL Functions with Ap- plications to Model Reduction,” IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, VOL.47, pp. 702-712, May 2000. [8] M. Tadeusiewicz and S. Halgas, “ An algorithm for finding all the DC solutions of short-channel mos transistors circuits,” Proceedings of the IEEE Inter- national Conference on Electronics, Circuits and Sys- tems, Jounieh, Lebanon 2000, pp.924-927. [9] M. Chien and E.Kuh, “Solving nonlinear resistive net- works using piecewise-linear analysis and simplicial subdivision,” IEEE Transactions on Circuits and Sys- tems, vol. 24, pp. 305–317, 1977. [10] H. Shichman and D. Hodges, “Modeling and simula- tion of insulated-gate field-effect transistor switching circuits”, IEEE J. Solid-State Circuits, VOL. SC-3, 1968, pp. 285-289. Ver+/- | |

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